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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\ddr3_1_4code_hs.v<br>
C:\Gowin\Gowin_V1.9.9_x64\IDE\ipcore\DDR3\data\ddr3_1_4code_hs\DDR3_TOP.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5AST-LV138PG484AES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5AST-138</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>B</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Wed Feb 21 02:52:32 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>DDR3_Memory_Interface_Top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.819s, Peak memory usage = 117.961MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 117.961MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.225s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.15s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.642s, Peak memory usage = 117.961MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.405s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 117.961MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.345s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 117.961MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.921s, Elapsed time = 0h 0m 3s, Peak memory usage = 124.125MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.368s, Peak memory usage = 124.125MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.481s, Peak memory usage = 133.102MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 6s, Peak memory usage = 133.102MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>667</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>659</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>327</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>291</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspTBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIOBUF</td>
<td>32</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspELVDS_OBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspELVDS_IOBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>5599</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>457</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>71</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>5070</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>3351</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>669</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>1521</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>1161</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>207</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>207</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>28</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>28</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>129</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIDES8_MEM</td>
<td>32</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOSER8</td>
<td>25</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOSER8_MEM</td>
<td>40</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIODELAY</td>
<td>32</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>24</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPX9B</td>
<td>16</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspCLKDIV</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDQS</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDDRDLL</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>3586(3379 LUT, 207 ALU) / 138240</td>
<td>3%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>5599 / 139095</td>
<td>5%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 139095</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>5599 / 139095</td>
<td>5%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>24 / 340</td>
<td>8%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>memory_clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>memory_clk_ibuf/I </td>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/n2461_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/n2461_s2/O </td>
</tr>
<tr>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.0</td>
<td>0.000</td>
<td>20.000</td>
<td>memory_clk_ibuf/I</td>
<td>memory_clk</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>memory_clk</td>
<td>100.0(MHz)</td>
<td>1448.7(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>clk</td>
<td>100.0(MHz)</td>
<td>234.5(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk</td>
<td>25.0(MHz)</td>
<td>168.4(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.613</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.748</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.361</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>memory_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.168</td>
<td>0.168</td>
<td>tCL</td>
<td>RR</td>
<td>5707</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.374</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/CLK</td>
</tr>
<tr>
<td>0.757</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_3_s0/Q</td>
</tr>
<tr>
<td>0.963</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/I0</td>
</tr>
<tr>
<td>1.542</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_3_s/F</td>
</tr>
<tr>
<td>1.748</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>memory_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>memory_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>memory_clk_ibuf/O</td>
</tr>
<tr>
<td>5.880</td>
<td>0.192</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>5.845</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td>5.361</td>
<td>-0.484</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[3].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.506</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.613</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.748</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.361</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>memory_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.168</td>
<td>0.168</td>
<td>tCL</td>
<td>RR</td>
<td>5707</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.374</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/CLK</td>
</tr>
<tr>
<td>0.757</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_2_s0/Q</td>
</tr>
<tr>
<td>0.963</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/I0</td>
</tr>
<tr>
<td>1.542</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_2_s/F</td>
</tr>
<tr>
<td>1.748</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>memory_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>memory_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>memory_clk_ibuf/O</td>
</tr>
<tr>
<td>5.880</td>
<td>0.192</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>5.845</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td>5.361</td>
<td>-0.484</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[2].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.506</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.613</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.748</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.361</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>memory_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.168</td>
<td>0.168</td>
<td>tCL</td>
<td>RR</td>
<td>5707</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.374</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/CLK</td>
</tr>
<tr>
<td>0.757</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_1_s0/Q</td>
</tr>
<tr>
<td>0.963</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/I0</td>
</tr>
<tr>
<td>1.542</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_1_s/F</td>
</tr>
<tr>
<td>1.748</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>memory_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>memory_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>memory_clk_ibuf/O</td>
</tr>
<tr>
<td>5.880</td>
<td>0.192</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>5.845</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td>5.361</td>
<td>-0.484</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[1].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.506</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.613</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.748</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>5.361</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>memory_clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.168</td>
<td>0.168</td>
<td>tCL</td>
<td>RR</td>
<td>5707</td>
<td>gw3_top/u_ddr_phy_top/fclkdiv/CLKOUT</td>
</tr>
<tr>
<td>0.374</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/CLK</td>
</tr>
<tr>
<td>0.757</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>9</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/read_rclksel_conf_0_s0/Q</td>
</tr>
<tr>
<td>0.963</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/I0</td>
</tr>
<tr>
<td>1.542</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_init/hold_Z_0_s/F</td>
</tr>
<tr>
<td>1.748</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/HOLD</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>memory_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>1</td>
<td>memory_clk_ibuf/I</td>
</tr>
<tr>
<td>5.688</td>
<td>0.688</td>
<td>tINS</td>
<td>FF</td>
<td>103</td>
<td>memory_clk_ibuf/O</td>
</tr>
<tr>
<td>5.880</td>
<td>0.192</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs/FCLK</td>
</tr>
<tr>
<td>5.845</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
<tr>
<td>5.361</td>
<td>-0.484</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/u_ddr_phy_wds/data_lane_gen[0].u_ddr_phy_data_lane/u_ddr_phy_data_io/u_dqs</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.506</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.579, 42.130%; route: 0.413, 30.027%; tC2Q: 0.382, 27.843%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.206, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.735</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.090</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.825</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clk[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>39</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>0.889</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/CLK</td>
</tr>
<tr>
<td>1.271</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/cs_memsync_5_s0/Q</td>
</tr>
<tr>
<td>1.477</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/n298_s6/I0</td>
</tr>
<tr>
<td>2.056</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/n298_s6/F</td>
</tr>
<tr>
<td>2.263</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s17/I0</td>
</tr>
<tr>
<td>2.841</td>
<td>0.579</td>
<td>tINS</td>
<td>RR</td>
<td>4</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s17/F</td>
</tr>
<tr>
<td>3.047</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s12/I1</td>
</tr>
<tr>
<td>3.615</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_0_s12/F</td>
</tr>
<tr>
<td>3.821</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s17/I3</td>
</tr>
<tr>
<td>4.110</td>
<td>0.289</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s17/F</td>
</tr>
<tr>
<td>4.316</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s11/I1</td>
</tr>
<tr>
<td>4.884</td>
<td>0.567</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_d_1_s11/F</td>
</tr>
<tr>
<td>5.090</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>39</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>10.889</td>
<td>0.206</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2/CLK</td>
</tr>
<tr>
<td>10.825</td>
<td>-0.064</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>gw3_top/u_ddr_phy_top/ddr_sync/flag_1_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 76.793%; route: 0.206, 23.207%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.581, 61.440%; route: 1.237, 29.456%; tC2Q: 0.382, 9.104%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 76.793%; route: 0.206, 23.207%</td></tr>
</table>
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